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PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 3 of 30
TXRATE
Character-Rate Clock
Bit-rate Clock
HML
TXCLKA
HML
HML
TXCLKB
TXCLKC
8
TXCTA[1:0]
TXDA[7:0]
TXOPA
8
TXCTB[1:0]
TXDB[7:0]
TXOPB
8
TXCTC[1:0]
TXDC[7:0]
TXOPC
TXPERA
TXPERB
2
2
2
TXPERC
HML
TXCLKD
8
TXCTD[1:0]
TXDD[7:0]
TXOPD
11
TXPERD
SCSEL
11
11
12
12
11
12
12
12
11
12
11
10
10
10
10
OUTA1+
OUTA1–
OUTA2+
OUTA2–
OUTB1+
OUTB1–
OUTB2+
OUTB2–
OUTC1+
OUTC1–
OUTC2+
OUTC2–
OUTD1+
OUTD1–
OUTD2–
SPDSEL
TXRST
TXMODE[1:0]
PARCTL
REFCLK+
REFCLK–
Transmit PLL
Clock Multiplier
Transmit
Mode
TXCLKO+
TXCLKO–
TXCKSEL
2
Transmit Path Block Diagram
BISTLE
OELE
BIST Enable
Latch
Output
Enable
4
8
Latch
BOE[7:0]
OUTD2+
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
TRSTZ