PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 10 of 30
to absorb clock phase differences between the presently
selected input clock and the internal character clock.
Initialization of the Phase-align Buffers takes place when the
TXRST input is sampled LOW by two consecutive rising edges
of REFCLK. When TXRST is returned HIGH, the present input
clock phase relative to REFCLK is set. TXRST is an
asynchronous input, but is sampled internally to synchronize
it to the internal transmit path state machines.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK;
i.e.,
±180°. This time shift allows the delay paths of the
character clocks (relative to REFCLK) to change due to
operating voltage and temperature, while not affecting the
design operation.
If the phase offset, between the initialized location of the input
clock and REFCLK
↑, exceeds the skew handling capabilities
of the Phase-align Buffer, an error is reported on the
associated TXPERx output. This output indicates a continuous
error until the Phase-align Buffer is reset. While the error
remains active, the transmitter for the associated channel will
output a continuous C0.7 character to indicate to the remote
receiver that an error condition is present in the link.
In specific transmit modes, it is also possible to reset the
Phase-align Buffers individually and with minimal disruption of
the serial data stream. When the transmit interface is
configured for generation of atomic Word Sync Sequences
(TXMODE[1] = MID) and a Phase-align Buffer error is present,
the transmission of a Word Sync Sequence will re-center the
Phase-align Buffer and clear the error condition.[5]
Parity Support
In addition to the ten data and control bits that are captured at
each transmit Input Register, a TXOPx input is also available
on each channel. This allows the CYP15G0401TB to support
ODD parity checking for each channel. Parity checking is
available for all operating modes (including Encoder Bypass).
The specific mode of parity checking is controlled by the
PARCTL input, and operates per Table 2.
When PARCTL is MID (open) and the Encoders are enabled
(TXMODE[1]
≠ LOW), only the TXDx[7:0] data bits are
checked for ODD parity along with the associated TXOPx bit.
When PARCTL = HIGH with the Encoder enabled (or MID with
the Encoder bypassed), the TXDx[7:0] and TXCTx[1:0] inputs
are checked for ODD parity along with the associated TXOPx
bit. When PARCTL = LOW, parity checking is disabled.
When parity checking and the Encoder are both enabled
(TXMODE[1]
≠ LOW), the detection of a parity error causes a
C0.7 character of proper disparity to be passed to the Transmit
Shifter. When the Encoder is bypassed (TXMODE[1] = LOW,
LOW), detection of a parity error causes a positive disparity
version of a C0.7 transmission character to be passed to the
Transmit Shifter.
Encoder
The character, received from the Input Register or Phase-align
Buffer and Parity Check Logic, is then passed to the Encoder
logic. This block interprets each character and any associated
control bits, and outputs a 10-bit transmission character.
Depending on the configured operating mode, the generated
transmission character may be
• the 10-bit pre-encoded character accepted in the Input
Register
• the 10-bit equivalent of the eight-bit Data character
accepted in the Input Register
• the 10-bit equivalent of the eight-bit Special Character code
accepted in the Input Register
• the 10-bit equivalent of the C0.7 SVS character if parity
checking was enabled and a parity error was detected
• the 10-bit equivalent of the C0.7 SVS character if a
Phase-align Buffer overflow or underflow error is present
• a character that is part of the 511-character BIST sequence
• a K28.5 character generated as an individual character or
as part of the 16-character Word Sync Sequence.
The selection of the specific characters generated are
controlled by the TXMODE[1:0], SCSEL, TXCTx[1:0], and
TXDx[7:0] inputs for each character.
Data Encoding
Raw data, as received directly from the Transmit Input
Register, is seldom in a form suitable for transmission across
a serial link. The characters must usually be processed or
transformed to guarantee
• a minimum transition density (to allow the remote serial
receive PLL to extract a clock from the data stream).
• a DC-balance in the signaling (to prevent baseline wander).
• run-length limits in the serial data (to limit the bandwidth
requirements of the serial link).
Notes:
4. The TXOPx inputs are also captured in the associated Input Register, but their interpretation is under the separate control of PARCTL.
5. One or more K28.5 characters may be added or lost from the data stream during this reset operation. When used with non-Cypress devices that require a complete
16-character Word Sync Sequence for proper Receive Elasticity Buffer alignment, it is recommend that the sequence be followed by a second Word Sync Sequence
to ensure proper operation.
6. Transmit path parity errors are reported on the associated TXPERx output.
7. Bits marked as X are XORed together. Result must be a logic-1 for parity to be valid.
Table 2. Input Register Bits Checked for Parity [6]
Signal
Name
Transmit Parity Check Mode (PARCTL)
LOW
MID
HIGH
TXMODE[1]
= LOW
TXMODE[1]
≠ LOW
TXDx[0]
X [7]
XX
TXDx[1]
X
X
X
TXDx[2]
X
X
X
TXDx[3]
X
X
X
TXDx[4]
X
X
X
TXDx[5]
X
X
X
TXDx[6]
X
X
X
TXDx[7]
X
X
X
TXCTx[0]
X
X
TXCTx[1]
X
X
TXOPx
X
X
X
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