CY28316
Document #: 38-07125 Rev. *B
Page 14 of 18
AC Electrical Characteristics (TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, fXTL = 14.31818 MHz)
AC clock parameters are tested and guaranteed over stated
operating conditions using the stated lump capacitive load at
the clock output; Spread Spectrum is disabled.
CPU Clock Outputs (CPUT0, CPUC0, CPU_CS)[8]
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
CPU = 133 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
tR
Output Rise Edge Rate
1.0
4.0
1.0
4.0
V/ns
tF
Output Fall Edge Rate
1.0
4.0
1.0
4.0
V/ns
tD
Duty Cycle
Measured at 50% point
45
55
45
55
%
tJC
Jitter, Cycle to Cycle
375
375
ps
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached
within 1 ms from power-up. Short
cycles exist prior to frequency
stabilization.
33
ms
Zo
AC Output Impedance
VO = VX
50
50
Ω
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Unit
tP
Period
Measured on the rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on the rising edge at 1.5V. Maximum difference of
cycle time between two adjacent cycles.
250
ps
tSK
Output Skew
Measured on the rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on the rising edge at
1.5V. CPU leads PCI output.
1.5
4
ns
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
30
Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by the crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on the rising and falling edges at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
Note:
8.
Refer to Figure 1 for K7 operation clock driver test circuit.
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