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IS25LP02GJ-RHLA3 Fiches technique(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS25LP02GJ-RHLA3 Fiches technique(HTML) 7 Page - Integrated Silicon Solution, Inc |
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7 / 182 page ![]() IS25LP02GJ IS25WP02GJ Integrated Silicon Solution, Inc.- www.issi.com 7 Rev.A 10/02/2025 1. PIN CONFIGURATION NC NC NC SCK GND VCC NC CE# NC WP#(IO2) NC SO(IO1) SI(IO0) HOLD# or RESET# (IO3) NC NC NC NC NC NC NC/WP# NC Top View, Balls Facing Down NC A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4 D1 D2 D3 D4 E1 E2 E3 E4 A5 B5 C5 D5 E5 (1) RESET#/NC (2) (2) (2) Notes: 1. The pin can be configured as Hold# or Reset# by setting P7 bit of the Read Register. Pin default is Hold# (IO3). 2. C4= IO2, and C5 = dedicated WP#, and A4 = RESET# in option W. 24-ball TFBGA 6x8x1.4mm (5x5 ball array) (Package: I) |
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