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LP5018 Fiches technique(PDF) 42 Page - Texas Instruments |
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LP5018 Fiches technique(HTML) 42 Page - Texas Instruments |
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42 / 59 page ![]() • Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board. • Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to prevent solder voids. 8.4.2 Layout Examples To LED To LED To LED To LED To LED To LED To LED To LED To LED To LED 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 GND OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT16 OUT17 OUT0 GND GND GND GND Figure 8-4. LP5018 VQFN Layout Example LP5018, LP5024 SLVSEB8C – OCTOBER 2018 – REVISED JULY 2024 www.ti.com 42 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: LP5018 LP5024 |
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