| Moteur de recherche de fiches techniques de composants électroniques |
|
TUSB1002AIRGET Fiches technique(PDF) 4 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TUSB1002AIRGET Fiches technique(HTML) 4 Page - Texas Instruments |
|
4 / 38 page ![]() Table 4-1. Pin Functions (continued) PIN TYPE INTERNAL PULLUP PULLDOWN DESCRIPTION NAME NO. CFG1 4 I (4-level) PU (approx 45K) PD (approx 95K) CFG1. This pin along with CFG2 selects the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options. CFG2 15 I (4-level) PU (approx 45K) PD (approx 95K) CFG2. This pin along with CFG1 sets the VOD linearity range and DC gain for both channels 1 and 2. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. Refer to Table 6-3 for VOD linearity range and DC gain options. MODE 7 I (4-level) PU (approx 45 K) PD (approx 95K) MODE. This pin is for selecting different modes of operation. The state of this pin is sampled after the rising edge of EN. Refer to Figure 5-2 for details of timing. 0 = Basic Redriver Mode. R = PCIe / Test Mode. PCIe Mode and TI Internal use only F = USB3.2 x1 Dual Channel Operation enabled (TUSB1002A normal mode). 1 = USB3.2 x1 Single-channel operation. RSVD1 24 O — RSVD1. Under normal operation, this pin is driven low by TUSB1002A. Recommend leaving this pin unconnected on PCB. DCBOOST # 14 I (2-level) PU (approx 400 K) DCBOOST#. This pin when asserted low increases the DC Gain level defined inTable 6-3 by +1dB unless already at +2dB. If DC Gain level defined inTable 6-3 is already at +2dB, then asserting this pin low will not change the DC Gain level. This pin can be left unconnected if this function is not needed. 1 = DC Gain defined by Table 6-3. 0 = DC Gain defined by Table 6-3 is increased by +1dB. VCC 1, 13 Power — 3.3V (±10%) Supply. GND 6, 10, 18, 21 GND — Ground Thermal pad — Thermal pad. Recommend connecting to a solid ground plane. TUSB1002A SLLSF63C – MARCH 2018 – REVISED JULY 2024 www.ti.com 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB1002A |
|
Lien URL |
| ALLDATASHEET vous a-t-il été utile ? [ DONATE ] |
À propos de Alldatasheet | Publicité | Contactez-nous | Politique de confidentialité | Lien vers la fiche technique | Echange de liens | Fabricants All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |