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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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NRF51822-CFAC-R Fiches technique(PDF) 20 Page - Nordic Semiconductor |
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NRF51822-CFAC-R Fiches technique(HTML) 20 Page - Nordic Semiconductor |
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20 / 130 page  Page 20 nRF51822 Product Specification v3.3 3 System blocks The chip contains system-level features common to all nRF51 Series devices including clock control, power and reset, interrupt system, Programmable Peripheral Interconnect (PPI), watchdog, and GPIO. System blocks which have a register interface and/or interrupt vector assigned are instantiated in the device address space. The instances of system blocks, their associated ID (for those with interrupt vectors), and base addresses are found in Table 18 on page 37. Detailed functional descriptions, configuration options, and register interfaces can be found in the nRF51 Series Reference Manual. 3.1 CPU The ARM® Cortex™-M0 CPU has a 16 bit instruction set with 32 bit extensions (Thumb-2® technology) that delivers high-density code with a small-memory-footprint. By using a single-cycle 32 bit multiplier, a 3-stage pipeline, and a Nested Vector Interrupt Controller (NVIC), the ARM Cortex-M0 CPU makes program execution simple and highly efficient. The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex-M processor series is implemented and available for M0 CPU. Code is forward compatible with ARM Cortex M3 based devices. |
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