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IS25LEG-RLLA2:P-TY Fiches technique(PDF) 158 Page - Integrated Silicon Solution, Inc

No de pièce IS25LEG-RLLA2:P-TY
Description  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  193 Pages
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Fabricant  ISSI [Integrated Silicon Solution, Inc]
Site Internet  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LEG-RLLA2:P-TY Fiches technique(HTML) 158 Page - Integrated Silicon Solution, Inc

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IS25LE01GG
IS25WE01GG
Integrated Silicon Solution, Inc.- www.issi.com
158
Rev. A3
10/02/2025
8.56 READ ASP OPERATION (RDASP, 2Bh)
The RDASP instruction code is shifted in by the rising edge of the SCK signal. Then the 16-bit ASP register contents
is shifted out, least significant byte first, most significant bit of each byte first. Each bit is shifted out at the SCK
frequency by the falling edge of the SCK signal. It is possible to read the ASP register continuously by providing
multiples of 16 bits.
Figure 8.127 Read ASP Sequence In SPI Mode
8
9
...
15
16
17
...
23
Instruction = 2Bh
CE#
SCK
SI
SO
0
1
2
3
4
5
6
7
Mode 3
Mode 0
tV
7
15
14
8
6
...
0
...
1st byte Data Out
2nd byte Data Out
Figure 8.128 Read ASP Sequence In QPI Mode
2Bh
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0
2
3
4
5
1st byte
Data Out
tV
2nd byte
Data Out



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