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IS25LEG-RLLA2:P-TY Fiches technique(PDF) 154 Page - Integrated Silicon Solution, Inc

No de pièce IS25LEG-RLLA2:P-TY
Description  SERIAL FLASH MEMORY 166/133MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  193 Pages
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Fabricant  ISSI [Integrated Silicon Solution, Inc]
Site Internet  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LEG-RLLA2:P-TY Fiches technique(HTML) 154 Page - Integrated Silicon Solution, Inc

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IS25LE01GG
IS25WE01GG
Integrated Silicon Solution, Inc.- www.issi.com
154
Rev. A3
10/02/2025
8.53 READ PPB OPERATION (RDPPB, FCh or 4RDPPB, E2h)
FCh (EXTADD=0) is followed by a 3-byte address (A23-A0) or
FCh (EXTADD=1) is followed by a 4-byte address (A31-A0) or
E2h is followed by a 4-byte address (A31-A0)
The instruction code is shifted into SI by the rising edges of the SCK signal, followed by the 24-bit or 32-bit address
selecting location zero within the desired sector/block as above. Then the 8-bit PPB Access Register contents are
shifted out on SO. The RDPPB/4RDPPB is supporting only SPI, not supporting QPI.
It is possible to read the same PPB Access Register continuously by providing multiples of eight bits. The address
of the PPB Access Register does not increment so this is not a means to read the entire PPB array. Each location
must be read with a separate Read PPB command.
Note: Data must be either 00h (protected) or FFh (unprotected).
Figure 8.119 Read PPB Sequence (FCh [EXTADD=0], 3-byte address)
Instruction = FCh
CE #
SCK
SI
SO
0
1
...
7
8
9
...
31
32
33
34
35
36
37
38
39
Mode 3
Mode 0
3-byte Address
tV
7
3
2
1
0
6
5
4
Figure 8.120 Read PPB Sequence (FCh [EXTADD=1] or E2h, 4-byte address)
Instruction = FCh/E2h
CE #
SCK
SI
SO
0
1
...
7
8
9
...
39
40
41
42
43
44
45
46
47
Mode 3
Mode 0
4-byte Address
tV
7
3
2
1
0
6
5
4



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