ICS40004AI01 datasheet(12/16 Pages) IDT

12 / 16 page

840004AGI-01

REV. A OCTOBER 22, 2007

ICS840004I-01

FEMTOCLOCKS™CRYSTAL-TO-

LVCMOS/LVTTL FREQUENCY SYNTHESIZER

LAYOUT GUIDELINE

Figure 4 shows a schematic example of the ICS840004I-

01. An example of LVCMOS termination is shown in this

schematic. Additional LVCMOS termination approaches are

shown in the LVCMOS Termination Application Note. In this

example, an 18pF parallel resonant 25MHz crystal is used.

FIGURE 4. ICS840004I-01 SCHEMATIC EXAMPLE

The C1=22pF and C2=22pF are recommended for fre-

quency accuracy. For different board layout, the C1 and C2

may be slightly adjusted for optimizing frequency accuracy.

Ω pullup or pulldown resistors can be used for the logic

control input pins.

100

RU1

Zo = 50 Ohm

100

Unused outputs can be left floating. There should be

no trace attached to unused outputs. Device

characterized and specification limits set with all

outputs terminated.

VDD

10uF

22pF

RU2

Not Install

RD2

0.1u

XTAL_IN

VDD

If not using the crystal input, it can be left floating.

For additional protection the XTAL_IN pin can be

tied to ground.

Logic Control Input Examples

VDDO

VDD

VDDA

Set Logic

Input to

'1'

840004i_01

F_SEL0

nXTAL_SEL

REF_CLK

nPLL_SEL

VDDA

VDD

XTAL_OUT

XTAL_IN

GND

VDDO

F_SEL1

GND

VDD

To Logic

Input

pins

LVCMOS

RD1

Not Install

22pF

VDD=3.3V

VDD

VDDO=3.3V

To Logic

Input

pins

0.1u

Optional Termination

Zo = 50 Ohm

XTAL_OUT

VDD

0.01u

LVCMOS

Set Logic

Input to

'0'

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