4. |Vhys| defines the minimum voltage separation between the actual |Vi| rising and falling thresholds.

5. A pullup resistor is present between the minus LVDS input and V3.3, and a pulldown resistor is present between plus LVDS

input and GND in order to force a ‘0’ value if the LVDS input is floating.

Table 12. Single-ended input and output signaling specifications (ISOSD61)

Parameter

Symbol

Min.

Typ.

Max.

Units

Conditions

Input high voltage

VIH

2

V

VDD = 3.3 V

VDD x 0.7

V

VDD = 5 V

Input low voltage

VIL

0.8

V

VDD = 3.3 V

VDD x 0.3

V

VDD = 5 V

Input current

IIND

±0.5

µA

Input capacitance

CIND

6

pF

Output high voltage

VOH

VDD – 0.06

VDD – 0.04

V

VDD = 5 V,

IOUT = -0.2 mA

VDD – 0.05

VDD – 0.03

VDD = 3.3 V,

IOUT = -0.2 mA

Output low voltage

VOL

0.01

0.02

V

IOUT = 0.2 mA

Table 13. Package characteristics

Parameter

Symbol

Min.

Typ.

Max.

Units

Test conditions

IC junction-to-ambient thermal

resistance

θJA

80

°C/W

On a 2s2p JEDEC board in free air as per

JEDEC JESD51, TA = 25°C

ISOSD61

Device specifications

DS13605 - Rev 11

page 9/23