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ICS1523MLF Fiches technique(PDF) 15 Page - Integrated Device Technology

No de pièce ICS1523MLF
Description  Video Clock Synthesizer with I2C Programmable Delay
PDF  21 Pages
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Fabricant  IDT [Integrated Device Technology]
Site Internet  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS1523MLF Fiches technique(HTML) 15 Page - Integrated Device Technology

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Video Clock Synthesizer with I2C Programmable Delay
MDS ICS1523 Z
15
Revision 052407
Integrated Device Technology, Inc.
Tech Support: www.idt.com/go/clockhelp
ICS1523
12.1 Timing for 0x0:2=0
Figure 12-2 0x0:2=0 Timing Diagram
Table 12-2
0x0:2=0 Timing Values
Symbol Parameter
Minimum
Typical
Maximum
Units
T2
HSYNC High to FUNC High
(DPA Offset = 0)
T8 + T3
ns
T3
HSYNC High to PECL CLK+ High
(DPA Offset = 0)
-7
-
ns
T4
PECL Clock Low to SSTL_3 Clock Low
Delay
00.2
0.6
ns
T5
PECL Clock Low to FUNC High Delay
0.6
1.0
1.6
ns
T6
PECL Clock Low to PECL/2 High Clock
0.6
1.0
1.6
ns
T7
PECL Clock Low to SSTL_3 CLK/2 Delay
0.4
0.9
1.2
ns
T8
PECL Clock High Time
-
0.5
-
UI



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