S-1155 datasheet(13/28 Pages) SII

No de pièce	S-1155

Description	HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

PDF	28 Pages

Scroll/Zoom	100%

Fabricant	SII [Seiko Instruments Inc]

Site Internet	http://www.sii.co.jp

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13 / 28 page

HIGH RIPPLE-REJECTION LOW DROPOUT HIGH OUTPUT CURRENT CMOS VOLTAGE REGULATOR

Rev.1.1_00

S-1155 Series

Seiko Instruments Inc.

Operation

1. Basic operation

Figure 11

shows the block diagram of the S-1155 Series.

The error amplifier compares the reference voltage (Vref) with Vfb, which is the output voltage resistance-divided by

feedback resistors Rs and Rf. It supplies the gate voltage necessary to maintain the constant output voltage which

is not influenced by the input voltage and temperature change, to the output transistor.

VOUT

VSS

VIN

Error amplifier

Current

supply

Vref

Vfb

−

Reference voltage

circuit

*1.

Parasitic diode

Figure 11

2. Output transistor

In the S-1155 Series, a low on-resistance P-channel MOS FET is used as the output transistor.

Be sure that VOUT does not exceed VIN

+ 0.3 V to prevent the voltage regulator from being damaged due to inverse

current which flows, because of a parasitic diode between the VIN and VOUT pin, when the potential of VOUT

became higher than VIN.

S-1155 Fiches technique(PDF) 13 Page - Seiko Instruments Inc