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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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L9908 Fiches technique(PDF) 77 Page - STMicroelectronics |
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L9908 Fiches technique(HTML) 77 Page - STMicroelectronics |
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77 / 152 page  Figure 50. Command edge triggering timing diagram The Tsync_flt can be set separately for each phase by the SPI signal TSYNCn_CFG<10:0> in the register CHn_CFG3, so that: TSYNCn=ΔLSB_TSYNC×TSYNCn_CFG10:0 (15) Being: ΔLSB_TSYNC=ΔACT_lsb (16) Where: ∆ACT_lsb is the ACT quantization step (see Table 98). 5.13.1.1.2 Auto-triggering Auto-triggering criteria relies on an internal counter which counts the number of clock cycles in which the sign comparator has the same sign. When the counted value equals the value configured in the CSMn_SYNC_COUNT_CFG register a trigger pulse is generated and the SAR conversion is performed. SAR conversion is launched independently of each current monitor, asynchronously. Note: Auto-triggering is always active and cannot be disabled. Its purpose is to allow A/D to promptly react in front of input voltage sharp transitions also in case command edge triggering is not enabled. SR counter threshold can be programmed for the single current monitor through the following SPI bits: L9908 Functional description DS13546 - Rev 5 page 77/152 |
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