L9826

Functional description

Doc ID 7214 Rev 10

13/19

5.2.2

Via 8-bit SPI for all the outputs

Control data are transmitted to SDI through a microcontroller in configuration master. The

device is selected when NCS signal is low. The 8-bit command data are transmitted into

L9826 shift registers every CLK falling edge (see Figure 6 for SPI signals timing).

The NCS rising edge latches the new data from the shift register to the driver and the output

are driven following the commands just sent.

The digital filter between NCS and the output latch ensures that the data are transferred

only after 8 CLK cycles or multiple of 8 CLK cycles since the last NCS falling edge.

The NCS changes only at low CLK.

Figure 5 shows the control register structure and in the detail its control-bit, while in the

Table 7 are summarized the controls outputs via SPI or dedicated input pins (NON1 and

NON2).

Figure 5.

Output control register structure

Figure 6.

Timing of the serial interface