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L9805E Fiches technique(PDF) 57 Page - STMicroelectronics |
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L9805E Fiches technique(HTML) 57 Page - STMicroelectronics |
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57 / 125 page ![]() L9805E On-chip peripherals 57/125 Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value) 1: An input capture has occurred.To clear this bit, first read the SR register, then read or write the low byte of the ICR2 (ICLR2) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value) 1: The content of the free running counter has matched the content of the OCR2 register. To clear this bit, first read the SR register, then read or write the low byte of the OCR2 (OCLR2) register. Bit 2-0 = Unused. INPUT CAPTURE 1 HIGH REGISTER (ICHR1) Timer1 Register Address: 0034h Timer2 Register Address: 0044h Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (ICLR1) Timer1 Register Address: 0035h Timer2 Register Address: 0045h Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 0 MSB LSB 7 0 MSB LSB |
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