MP1540 – 1.3MHz, 18V STEP-UP CONVERTER

MP1540 Rev. 1.0

www.MonolithicPower.com

6

8/15/2005

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© 2005 MPS. All Rights Reserved.

TM

Compensation

The MP1540 uses an amplifier to compensate

the feedback loop rather than a traditional

transconductance amplifier like most current

mode regulators. Frequency compensation is

provided by an internal resistor and capacitor

along with an external resistor. The system

uses two poles and one zero to stabilize the

control loop. The poles are fP1 set by the output

capacitor and load resistance, and fP2 set by the

internal compensation capacitor, the gain of the

error amplifier and the resistance seen looking

out at the feedback node REQ. The zero fZ1 is set

internally around 20KHz. These are determined

by the equations:

LOAD

1

P

R

2

C

1

f

×

×

π

=

()

EQ

9

2

P

R

10

9

.

7

2

1

f

×

×

×

π

×

=

−

KHz

20

f 1

Z =

Where RLOAD is the load resistance and REQ is:

)

2

R

1

R

(

)

2

R

1

R

(

3

R

REQ

+

×

+

=

Where R1, R2, and R3 are seen in Figure 2.

The DC loop gain is:

2

OUT

FB

LOAD

IN

VDC

V

V

R

V

500

A

×

×

×

=

There is also a right-half-plane zero (fRHPZ) that

exists in all continuous mode (inductor current

does not drop to zero on each cycle) step up

converters. The frequency of the right half plane

zero is:

2

OUT

LOAD

2

IN

RHPZ

V

L

2

R

V

f

×

×

π

×

×

=

To stabilize the regula tion control loop, the

crossover frequency (the frequency where the

loop gain dr ops to 0d B or a gain of 1, indicated

as fC) should be at least one decad e below the

right-half-plane zero and should b

e at most

75KHz. f RHPZ is a t it s lo west fr equency at

maximum o utput load current (R LOAD i s a t a

minimum) and minimum input voltage.

For the MP1540 it is re commended that a 4 7kΩ

to 100kΩ resistor be placed in series with the FB

pin and the resistor divider as se en in Figure 2.

For most applications this is all that is needed for

stable op eration. If g reater ph ase ma rgin is

needed a series r esistor and capacitor ca n be

placed in parallel with the high-side resistor R1 as

seen in Fi gure 2. The po le and ze ro se t b y the

lead-lag compensation network are:

⎟

⎟

⎟

⎟

⎠

⎞

⎜

⎜

⎜

⎜

⎝

⎛

+

+

+

×

×

π

×

=

3

R

1

2

R

1

1

R

1

1

4

R

3

C

2

1

f 3

P

()

4

R

1

R

3

C

2

1

f 2

Z

+

×

×

π

×

=

Layout Considerations

High frequ ency switching regulators require

very careful layout for stable operation and low

noise. All components must be p laced as close

to the IC as possible.

Keep the path betwee n

L1, D1, and C2 ex

tremely short for minimal

noise and r inging. C1 must be p laced clo se t o

the IN pin

for best decoupling.

All feedback

components must be kept close to the FB pin to

prevent noise injection o n the FB pin trace. The

ground return of C1 and C2 should be tied

close to the GND pin.