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LP3892 Fiches technique(PDF) 2 Page - Texas Instruments |
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LP3892 Fiches technique(HTML) 2 Page - Texas Instruments |
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2 / 19 page ![]() GND VIN S/D 1 2 3 4 8 7 6 5 VBIAS GND VOUT N/C GND VOUT LP3892 SNVS236D – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220, Top View Figure 2. DDPAK/TO-263, Top View Figure 3. SO PowerPAD-8, Top View white space white space white space white space BLOCK DIAGRAM 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3892 |
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