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CD54HC273F Fiches technique(PDF) 6 Page - Texas Instruments

No de pièce CD54HC273F
Description  CDx4HC(T)273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset
PDF  23 Pages
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Fabricant  TI2 [Texas Instruments]
Site Internet  https://www.ti.com
Logo TI2 - Texas Instruments

CD54HC273F Fiches technique(HTML) 6 Page - Texas Instruments

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5.4 Electrical Characteristics (continued)
PARAMETER
TEST
CONDITIONS
(2)
VCC (V)
25
℃
–40
℃ to 85℃
–55
℃ to 125℃
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
ΔICC (1)
Additional quiescent
device current per
input pin
CLR input held at
VCC –2.1
4.5 to
5.5
100
540
675
735
μA
Data inputs held at
VCC –2.1
4.5 to
5.5
100
144
180
196
μA
CLK inputs held at
VCC –2.1
4.5 to
5.5
100
540
675
735
μA
(1)
For dual-supply systems theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8mA.
(2)
VI = VIH or VIL, unless otherwise noted.
5.5 Prerequisite for Switching Characteristics
See Parameter Measurement Information
PARAMETER
VCC (V)
25
℃
–40
℃ to 85℃
–55
℃ to 125℃
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
HC TYPES
fMAX
Maximum clock frequency
2
6
5
4
MHz
4.5
30
25
20
6
35
29
23
tW
CLR pulse width
2
60
75
90
ns
4.5
12
15
18
6
10
13
15
tW
Clock pulse width
2
80
100
120
ns
4.5
16
20
24
6
14
17
20
tSU
Set-up time data to clock
2
60
75
70
ns
4.5
12
15
18
6
10
13
15
tH
Hold time, data to clock
2
3
3
3
ns
4.5
3
3
3
6
3
3
3
tREM
Removal time, CLR to clock
2
50
65
75
ns
4.5
10
13
15
6
9
11
13
HCT TYPES
fMAX
Maximum clock frequency
4.5
25
20
16
MHz
tw
CLR pulse width
4.5
12
15
18
ns
tw
Clock pulse width
4.5
20
25
30
ns
tSU
Set-up time data to clock
4.5
12
15
18
ns
tH
Hold time, data to clock
4.5
3
3
3
ns
tREM
Removal time, CLR to clock
4.5
10
13
15
ns
CD54HC273, CD74HC273
CD54HCT273, CD74HCT273
SCHS174C – FEBRUARY 1998 – REVISED JANUARY 2022
www.ti.com
6
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: CD54HC273 CD74HC273 CD54HCT273 CD74HCT273



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