STM32MP151AAC3 datasheet(1/245 Pages) STMICROELECTRONICS

No de pièce	STM32MP151AAC3

Description	Arm® Cortex®-A7 650 MHz Cortex®-M4 MPU, TFT, 35 comm. interfaces, 25 timers, adv. analog

PDF	245 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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1 / 245 page

This is information on a product in full production.

February 2019

DS12500 Rev 1

1/245

STM32MP151A

Arm® Cortex®-A7 650 MHz + Cortex®-M4 MPU,

TFT, 35 comm. interfaces, 25 timers, adv. analog

Datasheet

- production data

Features

Core

• 32-bit Arm® Cortex®-A7

– L1 32-Kbyte I / 32-Kbyte D

– 256-Kbyte unified level 2 cache

–Arm® NEON™ and Arm® TrustZone®

• 32-bit Arm® Cortex®-M4 with FPU/MPU

– Up to 209 MHz (Up to 703 CoreMark®)

Memories

• External DDR memory up to 1 Gbyte

– up to LPDDR2/LPDDR3-1066 16/32-bit

– up to DDR3/DDR3L-1066 16/32-bit

• 708 Kbytes of internal SRAM: 256 KB of AXI

SYSRAM + 384 KB of AHB SRAM + 64 KB of

AHB SRAM in backup domain and 4 KB of

SRAM in backup domain

• Dual mode Quad-SPI memory interface

• Flexible external memory controller with up to

16-bit data bus: parallel interface to connect

external ICs and SLC NAND memories with up

to 8-bit ECC

Security/safety

• TrustZone® peripherals, active tamper

• Cortex®-M4 resources isolation

Reset and power management

• 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)

• POR, PDR, PVD and BOR

• On-chip LDOs (RETRAM, BKPSRAM, USB

1.8 V, 1.1 V)

• Backup regulator (~0.9 V)

• Internal temperature sensors

• Low-power modes: Sleep, Stop and Standby

• LPDDR2/3 retention in Standby mode

• Controls for PMIC companion chip

Low-power consumption

• Total current consumption down to 6 µA

Clock management

• Internal oscillators: 64 MHz HSI oscillator,

4 MHz CSI oscillator, 32 kHz LSI oscillator

• External oscillators: 8-48 MHz HSE oscillator,

32.768 kHz LSE oscillator

• 5 × PLLs with fractional mode

General-purpose input/outputs

• Up to 176 I/O ports with interrupt capability

– Up to 8 secure I/Os

– Up to 6 Wakeup, 3 Tamper, 1 Active-

Tamper

Interconnect matrix

• 2 bus matrices

–64-bit Arm® AMBA® AXI interconnect, up to

266 MHz

–32-bit Arm® AMBA® AHB interconnect, up

to 209 MHz

3 DMA controllers to unload the CPU

• 48 physical channels in total

• 1 × high-speed general-purpose master direct

memory access controller (MDMA)

• 2 × dual-port DMAs with FIFO and request

router capabilities for optimal peripheral

management

LFBGA

TFBGA361 (12 × 12 mm)

TFBGA257 (10 × 10 mm)

min Pitch 0.5mm

TFBGA

LFBGA448 (18 × 18mm)

LFBGA354 (16 × 16mm)

Pitch 0.8mm

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