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STM32MP151AAB3 Fiches technique(PDF) 53 Page - STMicroelectronics |
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STM32MP151AAB3 Fiches technique(HTML) 53 Page - STMicroelectronics |
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53 / 245 page ![]() DS12500 Rev 1 53/245 STM32MP151A Functional overview 54 3.46 Gigabit Ethernet MAC interface (ETH1) The devices provide an IEEE-802.3-2002-compliant gigabit media access controller (GMAC) for Ethernet LAN communications through an industry-standard medium- independent interface (MII), a reduced medium-independent interface (RMII), a gigabit medium-independent interface (GMII) or a reduced gigabit medium-independent interface (RGMII). The STM32MP151A requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). The PHY is connected to the device port using 17 signals for MII, 7 signals for RMII, 26 signals for GMII or 13 signals for RGMII, and can be clocked using the 25 MHz (MII, RMII, GMII, RGMII) or 125 MHz (GMII, RGMII) from the STM32MP151A or from the PHY. The devices include the following features: • Operation modes and PHY interfaces – 10, 100, and 1000 Mbps data transfer rates – Support of both full-duplex and half-duplex operations – MII, RMII, GMII and RGMII PHY interfaces • Multiple queues support and audio video bridging (AVB) management – Separate channels or queues for AV data transfer in 100 and 1000 Mbps modes – Two queues on the Rx paths and two queues on the Tx path for AV traffic – One DMA for Rx path and two DMA for Tx path (one per transmit channels) – Several arbitration algorithms between queues: weighted round robin (WRR), strict priority (SP), weighted strict priority (WSP), IEEE 802.1-Qav specified credit- based shaper (CBS) algorithm for Transmit channels • Processing control – Multi-layer Packet filtering: MAC filtering on source (SA) and destination (DA) address with perfect and hash filter, VLAN tag-based filtering with perfect and hash filter, Layer 3 filtering on IP source (SA) or destination (DA) address, Layer 4 filtering on source (SP) or destination (DP) port – Double VLAN processing: insertion of up to two VLAN tags in transmit path, tag filtering in receive path – IEEE 1588-2008/PTPv2 support – Supports network statistics with RMON/MIB counters (RFC2819/RFC2665) • Hardware offload processing – Preamble and start-of-frame data (SFD) insertion or deletion – Integrity Checksum offload engine for IP header and TCP/UDP/ICMP payload: transmit checksum calculation and insertion, receive checksum calculation and comparison – Automatic ARP request response with the device's MAC address – TCP Segmentation: Automatic split of large transmit TCP packet into multiple small packets • Low-power mode – Energy efficient Ethernet (Standard IEEE 802.3az-2010) – Remote wakeup packet and AMD Magic Packet™ detection |
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