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ISO7641FCDWR Fiches technique(PDF) 29 Page - Texas Instruments |
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ISO7641FCDWR Fiches technique(HTML) 29 Page - Texas Instruments |
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29 / 37 page ![]() www.ti.com PACKAGE OUTLINE C TYP 10.63 9.97 2.65 MAX 14X 1.27 16X 0.51 0.31 2X 8.89 TYP 0.38 0.25 0 - 8 0.3 0.1 (1.4) 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 10.5 10.1 B NOTE 4 7.6 7.4 4221009/A 08/2013 SOIC - 2.65 mm max height DW0016B SOIC NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MO-013, variation AA. 1 16 0.25 C A B 9 8 PIN 1 ID AREA SEATING PLANE 0.1 C SEE DETAIL A TYPICAL DETAIL A SCALE 1.500 29 ISO7631FM, ISO7631FC, ISO7641FC www.ti.com SLLSEC3F – SEPTEMBER 2012 – REVISED APRIL 2016 Product Folder Links: ISO7631FM ISO7631FC ISO7641FC Submit Documentation Feedback Copyright © 2012–2016, Texas Instruments Incorporated |
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