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STM32F205RFT6 Fiches technique(PDF) 128 Page - STMicroelectronics |
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STM32F205RFT6 Fiches technique(HTML) 128 Page - STMicroelectronics |
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128 / 184 page ![]() Electrical characteristics STM32F20xxx 128/184 DocID15818 Rev 15 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 54 or Figure 55, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 54. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. |
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