ST72F324LK2T5 datasheet(52/154 Pages) STMICROELECTRONICS

No de pièce	ST72F324LK2T5

Description	3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

PDF	154 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

Logo

52 / 154 page

ST72324Lxx

52/154

MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (Cont’d)

Bit 0 = OIF Oscillator interrupt flag

This bit is set by hardware and cleared by software

reading the MCCSR register. It indicates when set

that the main oscillator has reached the selected

elapsed time (TB1:0).

0: Timeout not reached

1: Timeout reached

CAUTION: The BRES and BSET instructions

must not be used on the MCCSR register to avoid

unintentionally clearing the OIF bit.

MCC BEEP CONTROL REGISTER (MCCBCR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:2 = Reserved, must be kept cleared.

Bit 1:0 = BC[1:0] Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE-

HALT mode but has to be disabled to reduce the

consumption.

Table 16. Main Clock Controller Register Map and Reset Values

BC1

BC0

BC1

BC0

Beep mode with fOSC2=8MHz

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

Address

(Hex.)

Label

002Ch

MCCSR

Reset Value

MCO

CP1

CP0

SMS

TB1

TB0

OIE

OIF

002Dh

MCCBCR

Reset Value

BC1

BC0

ST72F324LK2T5 Fiches technique(PDF) 52 Page - STMicroelectronics

ST72F324LK2T5 Fiches technique(HTML) 52 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Fiches technique Télécharger

Lien URL