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LP3918TL/NOPB Fiches technique(PDF) 17 Page - Texas Instruments |
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LP3918TL/NOPB Fiches technique(HTML) 17 Page - Texas Instruments |
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17 / 38 page ![]() 60 ms PS_HOLD LDO1 LDO2 PWR_ON RESET LDO4,5,6 LDO3 LDO7 PWR_HOLD needs to be asserted while PWR_ON is high. 30 ms Debounce time Note: Serial I/F commands only take place after PS_HOLD is asserted. 87% Reg 87% Reg < 200 Ps RX_EN, TX_EN, TCXO_EN I2C Control LP3918 www.ti.com SNVS476D – AUGUST 2007 – REVISED MAY 2013 Device Power Up and Shutdown Timing Figure 4. Device Power Up Logic Timing. PWR_ON Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: LP3918 |
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