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74HCT240DB Fiches technique(PDF) 9 Page - NXP Semiconductors |
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74HCT240DB Fiches technique(HTML) 9 Page - NXP Semiconductors |
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9 / 17 page ![]() 74HC_HCT240 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 4 — 25 February 2016 9 of 17 NXP Semiconductors 74HC240; 74HCT240 Octal buffer/line driver; 3-state; inverting Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 8. Test circuit for measuring switching times Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC240 VCC 6ns 15pF, 50 pF 1k open GND VCC 74HCT240 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC |
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