FN8863 Rev.1.00

Page 5 of 25

Jul 27, 2017

ISL72028ASEH

1. Overview

1.2

Pin Configuration

1.3

Pin Descriptions

1.4

Equivalent Input and Output Schematic Diagrams

ISL72028ASEH

(8 Ld Ceramic Flatpack)

Top View

Pin

Number

Pin

Name

Function

1

D

CAN driver digital input. The bus states are LOW = dominant and HIGH = recessive. Internally tied HIGH.

2

GND

Ground connection

3

VCC

System power supply input (3.0V to 3.6V). The typical voltage for the device is 3.3V.

4

R

CAN data receiver output. The bus states are LOW = dominant and HIGH = recessive.

5

VREF

VCC/2 reference output for Split mode termination.

6

CANL

CAN bus line for low level output.

7

CANH

CAN bus line for high level output.

8

RS

A resistor to GND from this pin controls the rise and fall time of the CAN output waveform. Drive RS HIGH

to put the device in Low Power Shutdown mode.

Figure 3. CANH and CANL Inputs

Figure 4. CANH Output

Figure 5. CANL Output

D

GND

VCC

R

RS

CANH

CANL

VREF

8

7

6

5

2

3

4

1

Note: The package lid is tied to ground.

VCC

30V

INPUT

GND

2k

7k

4k

35k

VCC

30V

OUTPUT

GND

30V

OUTPUT

GND