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ADPL42002ACPZN1.8-R7 Fiches technique(PDF) 20 Page - Analog Devices

No de pièce ADPL42002ACPZN1.8-R7
Description  20V, 200mA, Low Noise, CMOS LDO Linear Regulator
PDF  22 Pages
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Fabricant  AD [Analog Devices]
Site Internet  http://www.analog.com
Logo AD - Analog Devices

ADPL42002ACPZN1.8-R7 Fiches technique(HTML) 20 Page - Analog Devices

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Data Sheet
ADPL42002
analog.com
Rev. 1
20 of 22
OUTLINE DIMENSIONS
Figure 35. 6-Lead Frame Chip Scale Package [LFCSP] 2mm x 2mm Body
and 0.55mm Package Height (CP-6-3) Dimensions shown in millimeters
Figure 36. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body (RD-8-1) Dimensions shown in millimeters
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
6
1
4
3
0.35
0.30
0.25
BOTTOM VIE W
PIN 1 INDEX
AREA
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.05 MAX
0.02 NOM
0.65 BSC
EXPOSED
PAD
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
2.10
2.00 SQ
1.90
0.15 MIN
SEATING
PLANE
PIN1
INDIC ATORAREAOPTIONS
(SEEDETAILA)
DETAIL A
(JEDEC 95)
TOP VIEW
SIDE VIEW
COMPLIANT TO JEDEC STANDARDS MS-012-AA
0.356
0.457
4.00
3.90
3.80
6.20
6.00
5.80
5.00
4.90
4.80
0.10 MAX
0.05 NOM
3.81 REF
45°
1.04 REF
8
1
4
5
1.75
1.35
1.65
1.25
2.39
2.29 SQ
2.19
0.51
0.31
0.50
0.25
1.27
0.40
0.25
0.17
COPLANARITY
0.10
1.27
BSC
BOTTOM VIEW
END VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
SEATING
PLANE
EXPOSED
PAD



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