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ST72F521 Fiches technique(PDF) 31 Page - STMicroelectronics

No de pièce ST72F521
Description  80/64-PIN 8-BIT MCU WITH 32 TO 60K FLASH/ROM, ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
PDF  215 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72F521 Fiches technique(HTML) 31 Page - STMicroelectronics

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SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Low Power Modes
6.4.3.1 Interrupts
The AVD interrupt event generates an interrupt if
the corresponding Enable Control Bit (AVDIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).
Mode
Description
WAIT
No effect on SI. AVD interrupts cause the
device to exit from Wait mode.
HALT
The CRSR register is frozen.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
AVD event
AVDF
AVDIE
Yes
No



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