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TMP19A71CYFG Fiches technique(PDF) 21 Page - Toshiba Semiconductor

No de pièce TMP19A71CYFG
Description  32-Bit RISC Microprocessor
PDF  402 Pages
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Fabricant  TOSHIBA [Toshiba Semiconductor]
Site Internet  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP19A71CYFG Fiches technique(HTML) 21 Page - Toshiba Semiconductor

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TMP19A71
3.4.4
When the SYNC Instruction Is Invalidated by an Interrupt
Even if the SYNC instruction is inserted to prevent possible problems as described in the
above examples, the SYNC instruction may be invalidated by an interrupt. The following
shows such a case occurring in the above example 2 (exiting standby mode).
Example 4: An interrupt invalidating the SYNC instruction
(Problem example)
ori
r26, r0, 0x0d
lui
r27, hi(TB0RUN)
sb
r26, lo(TB0RUN)(r27)
; Bit0 (TRUN) = 1 (timer start)
sync
; Stall until the timer starts counting.
; Omitted
; <---An interrupt occurs here. ----
lui
r27, hi(TB0RUN)
lb
r26, lo(TB0RUN)(r27)
; Save TB0RUN on the stack.
sb
r0 , lo(TB0RUN)(r27)
; Bit 0 (TRUN) = 0 (timer stop)
(Required processing)
sb
r26, lo(TB0RUN)(r27)
; Restore TB0RUN (timer restart).
ERET
; Omitted
; <---End of interrupt service routine----
wait
; Enter standby mode
nop
This problem can be avoided by inserting the SYNC instruction at the end of the
interrupt service routine (immediately before the ERET instruction).
TMP19A71 3-8



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