TMP88CS38 datasheet(13/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-13

System Control Register 1

SYSCR1

(00038H)

STOP

RELM

“0”

“1”

WUT

(Initial value: 0000 00** )

STOP

STOP mode start

0: CPU core and peripherals remain active

1: CPU core and peripherals are halted

(Start STOP mode)

RELM

Release method for STOP mode

STOP

edge-sensitive release (Rising edge)

STOP

level-sensitive release (“H” level)

Return to NORMAL mode

DV1CK

= 0

DV1CK

= 1

WUT

Warm-up time at releasing STOP

mode

× 216/fc

16/fc

14/fc

Reserved

× 217/fc

17/fc

15/fc

Reserved

R/W

Note 1:

Always set bit5 in SYSCR1 to “0”.

Note 2:

When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless of the

RETM contents.

Note 3:

fc: High-frequency clock [Hz], *: Don’t care

Note 4:

Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.

Note 5:

Always set bit4 in SYSCR1 to “1” when STOP mode is started.

System Control Register 2

SYSCR2

(00039H)

“1”

“0”

IDLE

(Initial value: 1000 **** )

IDLE

IDLE mode start

0: CPU and watchdog timer remain active

1: CPU and watchdog timer are stopped (Start IDLE mode)

R/W

Note 1:

*: Don’t care

Note 2:

Always set bit7, 6 and 5 in SYSCR2 to “100”.

Figure 1.4.8 System Control Registers

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