King Billion Electronics Co., Ltd.

駿

億

電

子

股

份

有

限

公

司

HE89C21

HE80000 SERIES

January 20, 2003

13

V1.0E

WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is

same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated

in Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1

clock has stopped.)

13. Low Voltage Reset

Low voltage reset circuit prevents the CPU from operating below its physical limit. When the supply

prevent CPU from bouncing back and forth between reset and operating state.

MO_LVR_LVL Detection voltage

Release voltage

00

1.9 volts

1.995 volts

01

2.0 volts

2.1 volts

10

2.1 volts

2.205 volts

The low voltage reset circuit can be disabled/enable by mask option MO_LVR_N.

MO_LVR_N LVR function

0

Enable

1

Disable

The voltage detection circuit is temperature compensated to prevent the detection voltage from drifting

with temperature variation.

Vdet

Vrst

VDD

Vrls

14. Dual-Tone Multiple Frequency Generator

The Dual-Tone Multiple Frequency (DTMF) generator is used to generate the Tone Dialing signal used in

Telecommunication applications. In fact, it can be used to generate any two channel sine wave signal with

frequency ranging from 1 ~ 2047 Hz with 1 Hz resolution. The DTMF generator derives its clock from

32768 Hz oscillator.