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ST10F273 Fiches technique(PDF) 21 Page - STMicroelectronics |
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ST10F273 Fiches technique(HTML) 21 Page - STMicroelectronics |
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21 / 179 page ![]() ST10F273 Functional description 21/179 3 Functional description The architecture of the ST10F273 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F273. Figure 3. Block diagram BRG BRG Port 6 Port 5 CPU-core and MAC unit XCAN2 XSSC XASC XCAN1 XI2C XRAM 2K XRAM 32K (16K STBY) (PEC) IFlash 512K 32 16 16 16 16 16 16 16 16 PEC Interrupt controller Port 3 Port 7 Port 8 16 Watchdog IRAM 2K 16 XRTC Oscillator PLL 5V-1.8V voltage regulator 16 16 8 816 15 8 8 16 16 32 kHz oscillator XPWM 16 16 |
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