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SH3003 Fiches technique(PDF) 16 Page - Semtech Corporation |
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SH3003 Fiches technique(HTML) 16 Page - Semtech Corporation |
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16 / 30 page ![]() 16 ©2006 Semtech Corp. SH3003 www.semtech.com Not authorized for release outside of Semtech - DRAFT POWER MANAGEMENT Application Information (continued) The SH3003 has two support modules that are specifi- cally designed for various real time support functions. They are the Real-Time Clock and the Periodic Interrupt / Wakeup Timer. Both of these units as well as other func- tions of the SH3003 depend on the internal 32.768kHz clock for accuracy. The SH3003 allows a trade-off between the cost of a sys- tem and its accuracy. For some devices, a single SH3003 without any support components provides sufficient ac- curacy. These units can operate with processor clock accuracy of ±0.5% and the accuracy of the real-time system of ±3%. At the other end of the spectrum, with one external com- ponent (a 32.768kHz crystal), the SH3003 can provide a processor clock accuracy of ±256ppm (±0.0256%) and the accuracy of the real-time system of ±4ppm (± 0.0004%). Real Time Support Special Operating Modes The SH3003 can operate stand-alone, without connec- tions to the In and Out terminals of the host’s oscillator. For example, a bank of SH3003 chips can generate sev- eral different frequencies for simultaneous use in the sys- tem, all controlled by a single micro (and possibly sharing one 32.768kHz crystal by chaining the CLK32 pin to XIN pin on the next device). In this case the CLKIN pin should be connected to VSS. The clock output on the CLKOUT pin is continuous; the correct operating mode is automatically recognized by the SH3003. A microcontroller may not have a STOP command. With the SH3003, this controller can do a “simulated” STOP by issuing an instruction to the SH3003 to stop the clock. This command is accepted only if the Periodic Interrupt / Wakeup Timer has started (otherwise, once the system is put to sleep, it would never wake up again). This mode of operations is only possible if the host processor is ca- pable of correct operations with clock frequency down to zero, and keeps all of the internal RAM alive while the clock is stopped. |
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