PPC405GP-3BE200CZ datasheet(49/59 Pages) AMCC

49 / 59 page

405GP – Power PC 405GP Embedded Processor

AMCC

Revision 2.03 – September 7, 2007

Data Sheet

Peripheral Interface Clock Timings

Parameter

Min

Max

Units

PCIClk input frequency (asynchronous mode)

Note 1

66.66

MHz

PCIClk period (asynchronous mode)

Note 1

PCI Clock frequency (synchronous mode)

33.33

MHz

PCI Clock period (synchronous mode - Note 2)

PCIClk input high time

40% of nominal period

60% of nominal period

PCIClk input low time

40% of nominal period

60% of nominal period

EMCMDClk output frequency

–

2.5

MHz

EMCMDClk period

400

–

EMCMDClk output high time

160

–

EMCMDClk output low time

160

–

PHYTxClk input frequency

2.5

MHz

PHYTxClk period

400

PHYTxClk input high time

35% of nominal period

–

PHYTxClk input low time

35% of nominal period

–

PHYRxClk input frequency

2.5

MHz

PHYRxClk period

400

PHYRxClk input high time

35% of nominal period

–

PHYRxClk input low time

35% of nominal period

–

PerClk output frequency–133MHz

–

33.33

MHz

PerClk period–133MHz

–

PerClk output frequency–200MHz

–

MHz

PerClk period–200MHz

–

PerClk output frequency–266MHz

–

66.66

MHz

PerClk period–266MHz

–

PerClk output high time

45% of nominal period

55% of nominal period

PerClk output low time

45% of nominal period

55% of nominal period

PerClk clock edge stability (phase jitter, cycle to cycle)

± 0.3

UARTSerClk input frequency (Note 3)

–

1000/(2TOPB+2ns)

MHz

UARTSerClk period

2TOPB+2

–ns

UARTSerClk input high time

TOPB+1

–ns

UARTSerClk input low time

TOPB+1

–ns

TmrClk input frequency–133MHz

–

33.33

MHz

TmrClk period–133MHz

–

TmrClk input frequency–200MHz

–

MHz

TmrClk period–200MHz

–

TmrClk input frequency–266MHz

–

66.66

MHz

TmrClk period–266MHz

–

TmrClk input high time

40% of nominal period

60% of nominal period

TmrClk input low time

40% of nominal period

60% of nominal period

Note:

1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded Processor

User’s Manual for more information.

2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.

3. TOPB is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for 266MHz

parts.

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