(Preliminary)

PL610-01

1.8V to 3.3V, 1MHz to 130MHz XO IC

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 4/2/07 Page 4

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB design:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper

termination this will cause reflections (looks like

ringing).

- Design long traces as “striplines” or “microstrips” with

defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible to

the VDD pin(s) to limit noise from the power supply

- Multiple VDD pins should be decoupled separately

for best performance.

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency

dependant. Typical values to use are 0.1

F for

designs using crystals < 50MHz and 0.01

F for

designs using crystals > 50MHz.

Series and parallel capacitors used to fine tune the crystal load to the circuit load.

– Series Capacitor, used to lower circuit load to match crystal load. Raises frequency

offset. This can be eliminated by using a crystal with a Cload of equal or greater value than the

oscillator.

– Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers

frequency offset.

Crystal

XIN

1

8

XOUT

Cpt

Cpt

Cst