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PRELIMINARY
CY7B9945V
Document Number: 38-07336 Rev. *F
Page 9 of 11
AC Test Loads and Waveform
Figure 3. AC Test Loads and Waveforms [22]
AC Timing Diagram
Figure 4. AC Timing Diagram
.
2.0V
0.8V
3.3V
GND
2.0V
0.8V
3.3V
OUTPUT
(a) LVTTL AC Test Load
< 1ns
< 1 ns
(b) TTL Input Test Waveform
R1
R2
CL
R1 = 910
Ω
R2 = 910 Ω
CL <30 pF
(Includes fixture and
probe capacitance)
R1 = 100
Ω
R2 = 100
Ω
CL < 25 pF to 185 MHz
For LOCK output only
For all other outputs
or 10 pF at 200 MHz
tPWL
tPWH
REF
FB
Q
tREFpwh
tREFpwl
tPD
tCCJ1-3,4-12
[1:2]Q[0,2]
tSKEWPR
[1:2]Q[0:3]
[1:2]Q[0:3]
tSKEWBNK
tSKEWPR
tSKEWBNK
Q
Other Q
tSKEW0,1
tSKEW0,1
2.0V
0.8V
tODCV
tODCV
REF TO DEVICE 1 and 2
FB DEVICE1
FB DEVICE2
tPD
tPDELTA
tPDELTA
[1:2]Q[1,3]
Notes
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that affects these parameters.
15. Rise and fall times are measured between 2.0V and 0.8V.
16. fNOM must be within the frequency range defined by the same FS state.
17. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
18. UI = unit interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
19. Measured at 0.5V deviation from starting voltage.
20. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz
21. These figures are for illustration purposes only. The actual ATE loads may vary.
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