AD7679ACPRL datasheet(21/28 Pages) AD

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AD7679

MASTER SERIAL INTERFACE

In Read during Conversion mode, the serial clock and data

toggle at appropriate instants, minimizing potential feedthrough

between digital activity and critical conversion decisions.

Internal Clock

The AD7679 is configured to generate and provide the serial

data clock SCLK when the EXT/INT pin is held low. The

AD7679 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted if desired. Depending on the

RDC/SDIN input, the data can be read after each conversion or

during the following conversion. Figure 38 and Figure 39 show

the detailed timing diagrams of these two modes.

In Read after Conversion mode, it should be noted that unlike

in other modes, the BUSY signal returns low after the 18 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

To accommodate slow digital hosts, the serial clock can be

slowed down by using DIVSCLK.

Usually, because the AD7679 is used with a fast throughput, the

mode master read during conversion is the most recommended

serial mode.

BUSY

CS, RD

CNVST

SYNC

SCLK

SDOUT

D17

D16

EXT/INT = 0

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

t14

t20

t15

t16

t22

t23

t29

t28

t18

t19

t21

t30

t25

t24

t26

t27

03085-0-040

Figure 38. Master Serial Data Timing for Reading (Read after Convert)

Rev. 0 | Page 21 of 28

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