PIC16F010-ESLASHMCSQTP datasheet(58/116 Pages) MICROCHIP

58 / 116 page

PIC12F510/16F506

DS41268C-page 56

Preliminary

CONFIG: CONFIGURATION WORD REGISTER (PIC12F510)

—

bit 15

bit 8

—

IOSCFS

MCLRE

WDTE

FOSC1

FOSC0

bit 7

bit 0

bit 15-6

Unimplemented: Read as ‘1’

bit 5

IOSCFS: Internal Oscillator Frequency Select bit

= 8 MHz INTOSC speed

= 4 MHz INTOSC speed

bit 4

MCLRE: Master Clear Enable bit

= GP3/MCLR pin functions as MCLR

= GP3/MCLR pin functions as GP3, MCLR internally tied to VDD

bit 3

CP: Code Protection bit

= Code protection off

= Code protection on

bit 2

WDTE: Watchdog Timer Enable bit

= WDT enabled

= WDT disabled

bit 1-0

FOSC<1:0>: Oscillator Selection bits

= LP oscillator with 18 ms DRT

= XT oscillator with 18 ms DRT

= INTOSC with 1.125 ms DRT(1), (2)

= EXTRC with 1.125 ms DRT(1), (2)

Note 1: Refer to the “PIC12F510 Memory Programming Specification”, DS41257 to determine how to access the

Configuration Word.

2: It is the responsibility of the application designer to ensure the use of the 1.125 ms (nominal) DRT will

result in acceptable operation. Refer to Electrical Specifications for VDD rise time and stability requirements

for this mode of operation.

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