38D5 datasheet(13/141 Pages) RENESAS

13 / 141 page

Rev.3.01

Aug 08, 2007

Page 13 of 134

REJ03B0158-0301

38D5 Group

Fig. 7 Register push and pop at interrupt generation and subroutine call

Interrupt request

→

On-going Routine

M(S) ← (PCH)

(S) ← (S)

− 1

M(S) ← (PCL)

(S) ← (S)

− 1

Execute RTS

Subroutine

(S) ← (S) + 1

(PCL) ← M(S)

(S) ← (S) + 1

(PCH) ← M(S)

M(S) ← (PCH)

(S) ← (S)

− 1

M(S) ← (PCL)

(S) ← (S)

− 1

M(S) ← (PS)

(S) ← (S)

− 1

Interrupt Service

Routine

(S) ← (S)

+ 1

(PS) ← M(S)

(S) ← (S)

+ 1

(PCL) ← M(S)

(S) ← (S)

+ 1

(PCH) ← M(S)

Execute JSR

Execute RTI

(1)

Push return address

on stack

Push contents of processor

status register on stack

I Flag is set from “0” to “1”

Fetch the jump vector

POP contents of

processor status

POP return

address

from stack

POP return address

from stack

Push return address

on stack

Note1: Condition for acceptance of an interrupt request here

→ Interrupt disable flag is “0” and

Interrupt enable bit corresponding to each interrupt source is “1”

Table 7

Push and pop instructions of accumulator or processor status register

Push instruction to stack

Pop instruction from stack

Accumulator

PHA

PLA

Processor status register

PHP

PLP

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