1996 Jan 12

13

Philips Semiconductors

Product specification

YUV 8-bit analog-to-digital interface

TDA8753A

The output data is valid 15 clock periods after WE goes HIGH.

handbook, full pagewidth

MBE430

12

3

15

t su

CLK

WE

data

t hd

output data valid

Fig.7 Set-up and hold time definition; WE signal.

Fig.8 Timing diagram; WE signal.

When the WE period is a whole multiple of 15 clock periods, the output data is valid without any clock delay.

The internal circuit always gives an internal 15 clock period as illustrated in Fig.7.

handbook, full pagewidth

MBE431

t su

CLK

WE

data

output data valid

K x 15 x periods