ADAU1361BCPZ-R7 datasheet(37/78 Pages) AD

No de pièce	ADAU1361BCPZ-R7

Description	Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL

PDF	78 Pages

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Fabricant	AD [Analog Devices]

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37 / 78 page

Data Sheet

ADAU1361

CONTROL PORTS

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Rev. E | 37 of 78

user should only issue one start condition, one stop condition, or

a single stop condition followed by a single start condition. If an

invalid subaddress is issued by the user, the ADAU1361 does not

issue an acknowledge and returns to the idle condition.

If the user exceeds the highest subaddress while in auto-increment

mode, one of two actions is taken. In read mode, the ADAU1361

outputs the highest subaddress register contents until the main

device issues a no acknowledge, indicating the end of a read. A

no acknowledge condition is where the SDA line is not pulled low

on the ninth clock pulse on SCL. If the highest subaddress location

is reached while in write mode, the data for the invalid byte is not

loaded into any subaddress register, a no acknowledge is issued by

the ADAU1361, and the part returns to the idle condition.

Figure 48. I2C Write to ADAU1361 Clocking

Figure 49. I2C Read from ADAU1361 Clocking

ADAU1361BCPZ-R7 Fiches technique(PDF) 37 Page - Analog Devices