±10%)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

High-Level Input Voltage

2.0

V

Low-Level Input Voltage

-0.3

+0.8

V

High-Level Output Voltage

V

Low-Level Output Voltage

0.4

V

Input Leakage Current

1.0

10

µA

MCK

Master Clock frequency

(Note 1)

26

MHz

Master Clock Duty Cycle

(high time/cycle time)

40

60

%

Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.

7

6

8

15

10

AUDIO

DATA

PROCESSOR

RESET

CONTROL

11

9

RST

16

V

U

SBF

SBC

SDATA

SCK

FSYNC

8 DEDICATED C.S. BITS

EXTERNAL

CLOCK

5

MCK

STA020

+5V

19

VD+

GND

18

0.1

µF

SERIAL PORT

MODE SELECT

TRANSMITTER

CIRCUIT

M0

23

M1

22

M2

21

TXP

20

TXN

17

D99AU989A

DECODER

SUBCODE

PORT

CHANNEL

STATUS BITS

CONTROL

Figure 2. STA020D Typical Connection Diagram.

7

6

8

15

10

AUDIO

DATA

PROCESSOR

µCONTROLLER

or

UNUSED

CHANNEL

STATUS BITS

CONTROL

11

9

RST

16

V

U

C

CBL

SDATA

SCK

FSYNC

8 DEDICATED C.S. BITS

EXTERNAL

CLOCK

5

MCK

STA020

+3.3V

19

VD+

GND

TRNPT

24

18

0.1

µF

SERIAL PORT

MODE SELECT

TRANSMITTER

CIRCUIT

M0

23

M1

22

M2

21

TXP

20

TXN

17

D97AU600A

Figure 1. STA020D Professional & Consumer Modes Typical Connection Diagram.

STA020D

4/11