24LC41A-SLASHP datasheet(4/18 Pages) MICROCHIP

4 / 18 page

24LC41A

DS21176D-page 4

 2003 Microchip Technology Inc.

2.0

FUNCTIONAL DESCRIPTION

2.1

DDC Monitor Port

The DDC Monitor Port operates in two modes, the

Transmit-only mode and the Bidirectional mode. There

is a separate 2-wire protocol to support each mode,

each having a separate clock input and sharing a

common data line (DSDA). The device enters the

Transmit-only mode upon power-up. In this mode, the

device transmits data bits on the DSDA pin in response

to a clock signal on the VCLK pin. The device will

remain in this mode until a valid high-to-low transition is

placed on the DSCL input. When a valid transition on

DSCL is recognized, the device will switch into the

Bidirectional mode and look for its control byte to be

sent by the master. If it detects its control byte, it will

stay in the Bidirectional mode. Otherwise, it will revert

to the Transmit-only mode after it sees 128 VCLK

pulses.

2.1.1

TRANSMIT-ONLY MODE

The device will power-up in the Transmit-only mode

at address 00H. This mode supports a unidirectional

2-wire protocol for transmission of the contents of the

memory array.

This device requires that it be initialized prior to valid

data being sent in the Transmit-only mode (see

Section 2.1.2 “Initialization Procedure”).

In this

mode, data is transmitted on the DSDA pin in 8-bit

bytes, each followed by a ninth, null bit (see Figure 2-

1). The clock source for the Transmit-only mode is

provided on the VCLK pin, and a data bit is output on

the rising edge on this pin. The eight bits in each byte

are transmitted by Most Significant bit first. Each byte

within the memory array will be output in sequence.

When the last byte in the memory array is transmit-

ted, the output will wrap around to the first location

and continue. The Bidirectional mode Clock (DSCL)

pin must be held high for the device to remain in the

Transmit-only mode.

2.1.2

INITIALIZATION PROCEDURE

After VCC has stabilized, the device will be in the

Transmit-only mode. Nine clock cycles on the VCLK pin

must be given to the device for it to perform internal

sychronization. During this period, the DSDA pin will be

in a high-impedance state. On the rising edge of the

tenth clock cycle, the device will output the first valid

data bit which will be the Most Significant bit of a byte.

The device will power-up at an indeterminate byte

address (Figure 2-2).

FIGURE 2-1:

TRANSMIT-ONLY MODE

FIGURE 2-2:

DEVICE INITIALIZATION

SCL

SDA

VCLK

TVAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB)

Bit 7

TVLOW

TVHIGH

TVAA

Bit 8

Bit 7

High-impedance for 9 clock cycles

TVPU

SCL

SDA

VCLK

VCC

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