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LP5526TL Fiches technique(PDF) 22 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
No de pièce LP5526TL
Description  Lighting Management Unit with High Voltage Boost Converter with up to 150mA Serial FLASH LED Driver
PDF  33 Pages
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Fabricant  NSC [National Semiconductor (TI)]
Site Internet  http://www.national.com
Logo NSC - National Semiconductor (TI)

LP5526TL Fiches technique(HTML) 22 Page - National Semiconductor (TI)

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General Purpose I/O Functionality
LP5526 has three general purpose I/O pins: GPIO[0]/PWM,
GPIO[1] and GPIO[2]. GPIO[0]/PWM can also be used as a
PWM input for the external LED PWM controlling. GPIO
bi-directional drivers are operating from the V
DDIO supply
domain.
Registers for GPIO are as follows:
GPIO CONTROL (06H)
Name
Bit
Description
EN_PWM_PIN
4
Enable PWM pin
0 = disable
1 = enable
OEN[2:0]
2:0
GPIO pin direction
0 = input
1 = output
GPIO DATA (07H)
Name
Bit
Description
DATA[2:0]
2:0
Data bits
GPIO control register is used to set the direction of each
GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data de-
fined DATA0 in GPIO data register. Note, that the EN_PW-
M_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to
act as PWM input. GPIO[1] and GPIO[2] pins can be se-
lected to be inputs or outputs, defined by OEN1 and OEN2
bit status. PWM functionality is valid only for GPIO[0]/PWM
pin. GPIO data register contains the data of GPIO pins.
When output direction is selected to GPIO pin, then GPIO
data register defines the output pin state. When GPIO data
register is read, it contains the state of the pin despite of the
pin direction.
Logic Interface Characteristics
(V
DDIO = 1.65V...VDD1,2 unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOGIC INPUT SCL, SDA, GPIO[0:2]
V
IL
Input Low Level
0.2xV
DDIO
V
V
IH
Input High Level
0.8xV
DDIO
V
I
I
Logic Input Current
−1.0
1.0
µA
f
SCL
Clock Frequency
400
kHz
LOGIC INPUT NRST
V
IL
Input Low Level
0.5
V
V
IH
Input High Level
1.2
V
I
I
Input Current
-1.0
1.0
µA
t
NRST
Reset Pulse Width
10
µs
LOGIC OUTPUT SDA
V
OL
Output Low Level
I
SDA = 3mA
0.3
0.5
V
V
OH
Output High Level
I
SDA = -3mA
V
DDIO − 0.5
V
DDIO − 0.3
I
L
Output Leakage Current
V
SDA = 2.8V
1.0
µA
LOGIC OUTPUT GPIO[0:2]
V
OL
Output Low Level
I
GPIO =3mA
0.3
0.5
V
V
OH
Output High Level
I
GPIO =-3mA
V
DDIO − 0.5
V
DDIO − 0.3
V
I
L
Output Leakage Current
V
GPIO = 2.8V
1.0
µA
www.national.com
22



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