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SC28L92 Fiches technique(PDF) 36 Page - NXP Semiconductors |
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SC28L92 Fiches technique(HTML) 36 Page - NXP Semiconductors |
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36 / 44 page ![]() Philips Semiconductors Product specification SC28L92 3.3V–5.0V Dual Universal Asynchronous Receiver/Transmitter (DUART) 2000 Jan 21 36 X1/CLK A1–A4 RWN CSN D0–D7 DTACKN tCSC tAS tCS tDF tDAT tDAH tCH tRWD tDD tDCR tAH DATA VALID NOT VALID tDA NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. SD00687 Figure 6. Bus Timing (Read Cycle) (68XXX mode) X1/CLK A1–A4 RWN CSN D0–D7 DTACKN tCSC tAS tCS tDH tDAT tDAH tCH tRWD tDS tDCW tAH NOTE: DACKN low requires two rising edges of X1 clock after CSN is low. SD00688 Figure 7. Bus Timing (Write Cycle) (68XXX mode) |
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