SST26VF032B-104ISLASHSM datasheet(38/82 Pages) MICROCHIP

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SST26VF032B/SST26VF032BA

DS20005218K-page 38

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5.36

Nonvolatile Write Lock Lock-Down

The nonvolatile Write Lock Lock-Down Register

(nVWLDR) instruction controls the ability to change the

Write Lock bits in the Block Protection register. Execute

WREN before initiating the nVWLDR instruction.

To execute nVWLDR, the host drives CE# low, then

sends the nVWLDR command cycle (E8H), followed by

18 cycles of data, and then drives CE# high.

After CE# goes high, the nonvolatile bits are pro-

grammed and the programming time-out must com-

plete before any additional commands, other than

Read STATUS Register, can be entered. Poll the BUSY

bit in the STATUS register, or wait TPP, for the comple-

tion of the internal, self-timed, Write operation. Data

inputs must be most significant bit(s) first.

FIGURE 5-42:

WRITE LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)

FIGURE 5-43:

WRITE LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)

Note:

MSN= Most Significant Nibble; LSN = Least Significant Nibble

Write Lock Lock-Down Register (nVWLDR) m = 79

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

H5 L5

HN LN

BPR [m:m-7]

BPR [7:0]

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

H5 L5

HN LN

BPR [m:m-7]

BPR [7:0]

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