XR-2212_06 datasheet(8/20 Pages) EXAR

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XR-2212

Rev. 2.10

R0=10K

R0=50K

R0=500K

R0=1MΩ

Ω

500K

50K

10K

Temperature (C)

+1.0

+0.5

-0.5

-1.0

-50

-25

100

125

VCC=12V

R1=12R0

f0=1kHz

Figure 9. Typical Center Frequency Drift vs. Temperature

DESCRIPTION OF CIRCUIT CONTROLS

Signal Input (Pin 2): Signal is AC coupled to this terminal.

The internal impedance at Pin 2 is 20k

W. Recommended

input signal level is in the range of 10mV to 5V

peak-to-peak.

VCO Current Output (Pin 3): This is a high impedance

W) current output terminal which can provide +100mA

drive capability with a voltage swing equal to VCC. This

output can directly interface with CMOS or NMOS logic

families.

VCO Voltage Output (Pin 5): This terminal provides a

low- impedance (

50W) buffered output for the VCO. It

can directly interface with low-power Schottley TTL. For

interfacing with standard TTL circuits, a 750

W pull-down

resistor from Pin 5 to ground is required. For operation of

the PLL without an external divider, Pin 5 can be DC

coupled to Pin 16.

Op Amp Compensation (Pin 6): The op amp section is

frequency compensated by connecting an external

capacitor from Pin 6 to the amplifier output (Pin 8). For

unity-gain

compensation

20pF

capacitor

recommended.

Op Amp Inputs (Pins 7 and 9): These are the inverting

and the non-inverting inputs for the op amp section. The

common-mode range of the op amp inputs is from +1V to

(VCC - 1.5) volts.

Op Amp Output (Pin 8): The op amp output is an open-

collector type gain stage and requires a pull-up resistor,

RL, to VCC for proper operation. For most applications, the

recommended value of RL is in 5kW to 10kW range.

Phase Detector Output (Pin 10): This terminal provides

a high-impedance output for the loop phase-detector. The

PLL loop filter is formed by R1 and C1 connected to Pin 10

(see

Figure 3). With no input signal, or with no

phase-error within the PLL, the DC level at Pin 10 is very

nearly equal to VREF. The peak voltage swing available at

the phase detector output is equal to

$VREF.

Reference Voltage, VREF (Pin 11): This pin is internally

biased at the reference voltage level. VREF:VREF = VCC/2

- 650mV. The DC voltage level at this pin forms an internal

reference for the voltage levels at Pins 10, 12 and 16. Pin

1 must be bypassed to ground with a 0.1

mF capacitor, for

proper operation of the circuit.

VCO Control Input (Pin 12): VCO free-running

frequencies determined by external timing resistor, R0,

connected from this terminal to ground. For optimum

temperature stability, R0 must be in the range of 10KW to

100k

W (see Figure 9).

VCO Frequency Adjustment: VCO can be fine-tuned

by connecting a potentiometer, RX, in series with R0 at Pin

12 (see

Figure 11).

This terminal is a low-impedance point, and is internally

biased at a DC level equal to VREF. The maximum timing

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