Philips Semiconductors

Preliminary specification

MIPS

PR31500

Poseidon embedded processor

1996 Sep 24

21

VIDEO

ITEM

PARAMETER

RISING/FALLING

LIMITS

UNIT

ITEM

PARAMETER

RISING/FALLING

MIN

MAX

UNIT

1

LOAD Pulse width

–

100

1600

ns

2

Delay LOAD Falling to FRAME

–

100

3200

ns

3

Delay LOAD Falling to DF

–

100

3200

ns

4

Delay LOAD Falling to CP

–

100

3200

ns

5

Delay CP Rising to VDAT[3:0]

–

–

3

ns

6

VDAT to CP Rising Setup

–

15

25

ns

7

VDAT to CP Rising Hold

–

15

25

ns

NOTE:

Values shown assume a 40MHz clock for the CPU, MIN and MAX values are programmable using Video Control Registers.

VIDEO TIMING DIAGRAMS

2

FRAME

1

LOAD

DF

3

CP

4

5

VDAT[3:0]

SN00179

Figure 12. Video Timing, 4 Bit Non-Split LCD

7

CP

VDAT[3:0]

6

SN00180

Figure 13. Video Data Timing, 4 Bit Split LCD and 8 Bit Non-Split LCD