56F8335 datasheet(74/160 Pages) FREESCALE

74 / 160 page

56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

5.6 Register Descriptions

A register address is the sum of a base address and an address offset. The base address is defined at the

system level and the address offset is defined at the module level. The ITCN peripheral has 24 registers.

Table 5-3 ITCN Register Summary

(ITCN_BASE = $00F1A0)

Acronym

Base Address +

Section Location

IPR0

Interrupt Priority Register 0

5.6.1

IPR1

Interrupt Priority Register 1

5.6.2

IPR2

Interrupt Priority Register 2

5.6.3

IPR3

Interrupt Priority Register 3

5.6.4

IPR4

Interrupt Priority Register 4

5.6.5

IPR5

Interrupt Priority Register 5

5.6.6

IPR6

Interrupt Priority Register 6

5.6.7

IPR7

Interrupt Priority Register 7

5.6.8

IPR8

Interrupt Priority Register 8

5.6.9

IPR9

Interrupt Priority Register 9

5.6.10

VBA

Vector Base Address Register

5.6.11

FIM0

Fast Interrupt 0 Match Register

5.6.12

FIVAL0

Fast Interrupt 0 Vector Address Low Register

5.6.13

FIVAH0

Fast Interrupt 0 Vector Address High Register

5.6.14

FIM1

Fast Interrupt 1 Match Register

5.6.15

FIVAL1

Fast Interrupt 1 Vector Address Low Register

5.6.16

FIVAH1

$10

Fast Interrupt 1 Vector Address High Register

5.6.17

IRQP0

$11

IRQ Pending Register 0

5.6.18

IRQP1

$12

IRQ Pending Register 1

5.6.19

IRQP2

$13

IRQ Pending Register 2

5.6.20

IRQP3

$14

IRQ Pending Register 3

5.6.21

IRQP4

$15

IRQ Pending Register 4

5.6.22

IRQP5

$16

IRQ Pending Register 5

5.6.23

Reserved

ICTL

$1D

Interrupt Control Register

5.6.30

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